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(2) Reverse channel
Pin
No.
Signal name I/O
direction
Pin No. Signal name I/O
direction
1 HostClk Input 19 HostClk-RET
2 DATA1 Input 20 DATA1-RET
3 DATA2 Input 21 DATA2-RET
4 DATA3 Input 22 DATA3-RET
5 DATA4 Input 23 DATA4-RET
6 DATA5 Input 24 DATA5-RET
7 DATA6 Input 25 DATA6-RET
8 DATA7 Input 26 DATA7-RET
9 DATA8 Input 27 DATA8-RET
10 PtrClk Output 28 PtrClk-RET
11 PtrBusy Output 29 PtrBusy-RET
12 AckDateReq Output 30 *INIT-RET
13 Xflag Output 31 *INIT Input
14 HostBusy Input 32 *DataAvail Output
15 N.C. 33 SG1 Output
16 SG1 34 DK_STATUS Output
17 FG 35 +5V Output
18 LOGIC-H Output 36 1284-Active Input
Notes:
1. Each -RET is connected to SG.
2. "*" indicates a negative-logic signal.
APPENDIX