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2.2 Lock Control Block
(2) State transition diagram at low power consumption mode
(a) When power-on reset option selected
(b) When power-on reset option not selected
(c) After oscillation stabilized
(d) Set STP bit to 1.
(e) Set SLP bit to 1.
(f) External reset when power-on reset option not selected
(g) External reset or interrupt when power-on reset option selected
(h) External reset or interrupt
Oscillation
stabilization waiting
(e)
(h)
(f)
(g)
(d)
(a) (b)
(c)
RUN
Clock oscillate
STOP
Clock stop
Power-on
SLEEP
Clock oscillate