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CHAPTER 2 HARDWARE CONFIGRATION
Second and later write
The watchdog timer can be stopped only by reset. 1111 is read when these bit are read.
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Description of Operation
(1) Starting watchdog timer
The watchdog timer starts when 0101 is written at the watchdog timer control bits.
(2) Clearing watchdog timer
When 0101 is written at the watchdog timer control bits after start, the watchdog timer is
cleared. The counter of the watchdog timer is cleared when changing to the standby mode
(STOP, SLEEP).
(3) Watchdog timer reset
If the watchdog timer is not cleared within the time given in the table below, a watchdog timer
reset occurs to reset the chip internally.
(4) Stopping watchdog timer
Once started, the watchdog timer will not stop until a reset occurs.
0101 Watchdog timer counter cleared
Other than the above No operation
Time-base timer cycle
2
21
/f
Minimum time Approx. 524 ms
Maximum time Approx. 1049 ms f : 4MHz