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2.3 Interrupt Controller
2.3 Interrupt Controller
• The interrupt controller for the F
2
MC-8L family is located between the CPU and each
resource. This controller receives interrupt requests from the resources, assigns
priority to them, and transfers the priority to the CPU. It also decides the priority of
same-level interrupts.
■
Block Diagram
■
Register List
Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3) and interrupt-test register
(ITR).
•
•
•
Resource #1
Resource #2
Resource #n
CPU
F
2
MC-8L bus
Address decorder
G L
Level
deciding
block
G
G
G
L
L
G
G
Interrupt vec-
tor generation
block
2
•
Same level
priority order
deciding block
Level
Level
Level
•
Test reg-
ister
Address: 007CH
Address: 007DH
Address: 007EH
Address: 007FH
ILR1
ILR2
ILR3
ITR
8 bit
W Interrupt level register #1
W Interrupt level register #2
W Interrupt level register #3
— Interrupt test register