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SCSI BUS
7-26 C156-E228-02EN
(3) Timeout procedure
If the TARG cannot detect a response from the INIT when the Selection Timeout
Delay or longer has passed in the RESELECTION phase, the timeout procedure
shall be performed though one of the following schemes:
1) The INIT asserts the RST signal to generate the RESET condition.
2) TARG terminates releasing SCSI ID to DATA BUS with maintaining SEL
signal and I/O signal in TRUE status. Subsequently, the INIT waits for the
response from TARG for at least Selection Abort Time + Deskew Delay × 2.
If no response is detected, the INIT releases the SEL signal allowing the SCSI
bus to go to the BUS FREE phase. If the INIT detects the response from
TARG during this period, the INIT considers the SELECTION phase to have
completed normally.
The ODD performs process 2) above as RESELECTION-phase time-out
processing.
7.6.5 INFORMATION TRANSFER phases
COMMAND, DATA, STATUS, and MESSAGE phases are generally called
INFORMATION TRANSFER phases. In these phases, data and control
information are transferred between the INIT and the TARG through the data bus.
The type of INFORMATION TRANSFER phase is determined by the
combination of C/D, I/O, and MSG signals (see Table 7.1). Since these three
signals are specified by the TARG, phase transition is controlled by the SCSI
device operating as a TARG. The INIT can request the TARG to initiate an
MESSAGE OUT phase by sending an ATN signal. Besides, the TARG can
change the bus phase to BUS FREE by ceasing transmission of the BSY signal.
Information transfer in an INFORMATION TRANSFER phase is controlled by
REQ and ACK signals. The REQ signal is sent by the TARG to request data
transfer, and the ACK signal is a response from the INIT. One pair of REQ and
ACK signals causes one byte of information to be transferred. According to the
method of sending an REQ signal and checking the replied ACK signal
(REQ/ACK handshake), two data transfer modes are defined: synchronous and
asynchronous.
During operation in an INFORMATION TRANSFER phase, the BSY signal must
be kept true by the TARG. The SEL signal must be false. The TARG must
establish the status of three signals C/D, I/O, and MSG which specify the phase
type at least Bus Settle Delay before the leading edge of the REQ signal which
requests transfer of the first byte. The TARG must maintain that status until the
trailing edge of the ACK signal corresponding to the last byte in the phase (see
Figure 7.13).