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EM78P221/2N
8-Bit Microcontroller with OTP ROM
14 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
6.2.17 Bank 1-R9 (Reserve)
Bits 7~0: not used, fixed to 0 all the time
6.2.18 Bank 1-RA (CMPCON: Comparator Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EIS1 EIS0 CMPOUT CMPCOS1 CMPCOS0 0 0 0
Bit 7 (EIS1): Control bit used to define the function of the P71 (/INT1) pin
0 = P71, normal I/O pin
1 = /INT1, external interrupt pin. In this case, the I/O control bit of P71
(Bit 1 of Bank 1-R7) must be set to "1"
Bit 6 (EIS0): Control bit used to define the function of the P77 (/INT0) pin
0 = P77, normal I/O pin
1 = /INT0, external interrupt pin. In this case, the I/O control bit of P77
(Bit 7 of Bank 1-R7) must be set to "1"
NOTE
When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT
pin can also be read by way of reading Port 7 (Bank 0-R7). Refer to Fig. 6-4 (I/O
Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1) under
Section 6.4 (I/O Ports).
EIS0 and EIS1 are both readable and writable.
The highest priority of P71/INT1/CO2 is INT1. When EIS1=0, the working type
of P71/INT1/CO is determined by CMPCOS1 and CMPCOS0.
Bit 5 (CMPOUT): The result of the comparator output
Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits
CMPCOS1 CMPCOS0 Function Description
0 0
Comparator is not used. P72, P73 and P71 are
normal I/O pins
0 1
P72 and P73 are Comparator input pins and P71
is normal I/O pin
1 0
P72 and P73 are Comparator input pins and P71
is Comparator output pin (CO)
1 1 Used as OP and P71 is OP output pin (CO)
Bits 2~0: not used, fixed to 0 all the time