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5308.3
45504550
128 MB262740-2070 (1513)
4270
36604550
128 MB262740-2070 (1512)
2333.3
20004550
128 MB262740-2070 (1511)
1225
10504550
128 MB262740-2070 (1510)
140
1204550
128 MB262740-2070 (Base)
4270
36603660
88 MB262740-2069 (1512)
2333.3
20003660
88 MB262740-2069 (1511)
1225
10503660
88 MB262740-2069 (1510)
140
1203660
88 MB262740-2069 (Base)
2333.3
20002890
84 MB262730-2068 (1511)
1225
10502890
84 MB262730-2068 (1510)
653.3
5602890
84 MB262730-2068 (1509)
280
2402890
84 MB262730-2068 (1508)
81.7
702890
84 MB262730-2068 (Base)
2333.3
20002000
44 MB262730-2067 (1511)
1225
10502000
44 MB262730-2067 (1510)
653.3
5602000
44 MB262730-2067 (1509)
280
2402000
44 MB262730-2067 (1508)
81.7
702000
44 MB262730-2067 (Base)
1225
10501050
24 MB262730-2066 (1510)
653.3
5601050
24 MB262730-2066 (1509)
280
2401050
24 MB262730-2066
(
1508
)
140
1201050
24 MB262730-2066
(
1507
)
81.7
701050
24 MB262730-2066
(
Base
)
653.3
560560
14 MB262730-2065
(
1509
)
280
240560
14 MB262730-2065
(
1508
)
140
120560
14 MB262730-2065
(
1507
)
81.7
70560
14 MB262730-2065
(
Base
)
1225
10501600
44 MB255720-2064
(
1505
)
653.3
5601600
44 MB255720-2064
(
1504
)
Interactive CPW
(Max)
Interactive CPW
(Knee)
Processor CPW
CPUs
L2 cache
per CPU
Chip Speed
MHz
Model
C.12.2 Model 170 Servers
Current 170 Servers
MAX Interactive CPW = Interactive CPW (Knee) * 7/6
CPU % used by Interactive @ Knee = Interactive CPW (Knee) / Processor CPW * 100
CPU % used by Processor @ Knee = 100 - CPU % used by Interactive @ Knee
CPU % used by Interactive @ Max = Max Interactive CPW / Processor CPW * 100
7.56.492.381.7
701090
4 MB255 MHz22388
17.815.284.881.7
70460
4 MB252 MHz12386
12.710.989.158.3
50460
4 MB252 MHz12385
15.913.686.435
30220
n/a200 MHz12292
25.421.778.329.2
25115
n/a200 MHz12291
3227.472.623.3
2073
n/a200 MHz12290
35307017.5
1550
n/a200 MHz12289
Interactive
CPU %
@ Max
Interactive
CPU %
@ Knee
Processor
CPU %
@ Knee
Interactive
CPW
(Max)
Interactive
CPW
(Knee)
Processor
CPW
L2 cache
per CPU
Chip
Speed
CPUsFeature #
Table C.12.2.1 Current Model 170 Servers
IBM i 6.1 Performance Capabilities Reference - January/April/October 2008
© Copyright IBM Corp. 2008 Appendix C CPW, CIW and MCU for System i Platform 362