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Networking Silicon — 82540EP
Datasheet 1
1.0 Introduction
The Intel
®
82540EP Gigabit Ethernet Controller is a single, compact component with an integrated
Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop,
workstation and mobile PC Network designs with critical space constraints, the Intel
®
82540EP
allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with
current generation 10/100 Mbps Fast Ethernet designs
The Intel
®
82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated,
physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T,
100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable
of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to
managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral
Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.
The 82540EP also incorporates the CLKRUN protocol and hardware supported downshift
capability to two or three-pair 100 Mb/s operation. These features optimize mobile applications.
The Intel
®
82540EP’s on-board System Management Bus (SMB) port enables network
manageability implementations required by information technology personnel for remote control
and alerting via the LAN. With SMB, management packets can be routed to or from a management
processor. The SMB port enables industry standards, such as Intelligent Platform Management
Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In
addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with
standardized interfaces.
The 82540EP Gigabit Ethernet Controller architecture is designed to deliver high performance and
PCI bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently
handling large address and data words. The 82540EP controller includes advanced interrupt
handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for
efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient
PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as
available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads
tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation.
The 82540EP is packaged in a 15 mm
2
196-ball grid array and is pin compatible with both the
82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller and the 82540EM
Gigabit Ethernet Controller (which does not have added power saving features like CLKRUN).