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82540EP — Networking Silicon
2 Datasheet
Figure 1. Gigabit Ethernet Controller Block Diagram
Tx
Arb
PCI
i/f
PCI I/F
RX MAC
TX MAC
TX
descriptor
engine
Data Alignment
FIFOs
PCI
Core
DMA
MAC Core
82540EP Architecture
Packet Buffer
Target
Control
Control, Status
& Interrupt
Registers
Target Logic
Filter
Statistics
Packet Buffer Interface
ACPI
TX
RX
RX
In
TX
Out
HW
Default
Configs
RX Data
TX
Link
MDI
(Copper)
Interface
4-wire EEPROM Interface
MDIOFlash
Flash Interface
Clock / Reset
EEPROM
Master
read
FIFO
Master
write
FIFO
RX
descriptor
engine
FIFOs
(Many
blocks)
64K bytes
LED
ASF
PHY
SMBus Interface
TX Data
RX Data
CSR Register
Access
CSR Register
Access
Mgmt
FIFOs
Manageability
Flow
Ctrl
GMII