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98 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Host Software Interface
The diagnose command checks the following internal device circuitry:
• Exponential backoff random number generator (linear feedback shift register).
• Exponential backoff time-out counter.
• Slot time period counter.
• Collision number counter.
• Exponential backoff shift register.
• Exponential backoff mask logic.
This procedure checks the operation of the backoff block, which resides in the serial side and is not
easily controlled. The CU triggers the self-test procedure of the serial subsystem. It performs the
following sequence:
1. Begins execution of the diagnose action command.
2. Waits for command completion.
3. Prepares the status word with the C bit equal to 1, OK equal to 1, and F equal to 0 if the
diagnose succeeded. Otherwise, the status word has the C bit equal to 1, OK equal to 0, and F
equal to 1.
4. Completes action command.
The CSMA/CD module performs the self test procedure in two phases: phase 1 tests the counters
and phase 2 tests the trigger logic.
Link Address
This is the 32-bit address of the next command block. It is added to the CU base to
obtain the actual address.
EL (Bit 31)
If this bit is set to one, it indicates that this command block is the last one on the CBL.
The CU will go from the active to the idle state after the execution of the CB is finished.
This transition will always cause an interrupt with the CNA/CI bit set in the SCB.
S (Bit 30)
If this bit is set to one, the CU will be suspended after the completion of this CB. A CNA
interrupt will be generated if the device is configured for this. The CU transitions from the
active to the suspended state after the execution of the CB.
I (Bit 29)
If the I bit is set to one, the device generates an interrupt after the execution of the CB is
finished. If I is not set to one, the CX interrupt will not be generated.
Bits 28:19 These bits are reserved and should all be set to 0.
CMD (Bits 18:16) This is the diagnose command, which has a value of 111b.
C (Bit 15)
This bit indicates the execution status of the command. Software should reset this bit
before issuing the command to the device. Following a command completion, the device
sets it to one.
NOTE: The difference in the definition of the C bit for the transmit command
(Section 6.4.2.5).
OK (Bit 13)
The OK bit indicates that the command was executed without error. If it equals one, no
error occurred (command executed OK). If the OK bit is zero and the C bit is set, then an
error occurred.
NOTE: The difference in the definition of the C bit for the transmit command
(Section 6.4.2.5).
F (Bit 11)
This bit indicates the results of the self-test procedure. A 0 indicates a pass, and a 1,
failure.