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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 51
Host Software Interface
b. Interrupt Enable (bit 29) = 1 or 0
c. Opcode (bits 27:26) = 01b (write)
d. PHYAdd = the PHY address from the MDI register
e. RegAdd = the register address of the specific register to be accessed (0 through 31)
f. Data = data to be written to the specified PHY register
2. The LAN controller shifts the following sequence out of the MDIO pin:
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>
3. The LAN controller asserts an interrupt indicating MDI is finished if the Interrupt Enable bit
was set.
4. The LAN Controller sets the Ready bit in the MDI register to indicate step 2 has been
completed.
5. The CPU may issue a new MDI command.
6.3.5.3 MDI Read cycle
The sequence of events for a MDI read cycle is:
1. The CPU performs a PCI write cycle to the MDI register with:
a. Ready (bit 28) = 0
b. Interrupt Enable (bit 29) = 1 or 0
c. Opcode (bits 27:26) = 10b (read)
d. PHYAdd = the PHY address from the MDI register
e. RegAdd = the register address of the specific register to be accessed (0 through 31)
2. The LAN controller shifts the following sequence out of the MDIO pin:
<PREAMBLE><01><10><PHYADD><REGADD><Z>
where Z = the LAN controller tri-stating the MDIO pin
3. The PHY shifts the following sequence out of the MDIO pin:
<0><DATA><IDLE>
4. The LAN controller discards the leading bit and places the following 16 data bits in the MDI
register.
5. The LAN Controller asserts an interrupt indicating MDI has completed if the Interrupt Enable
bit was set.
6. The LAN controller sets the Ready bit in the MDI register indicating the read is complete.
7. The CPU may read the data from the MDI register and issue a new MDI command.
6.3.6 Receive Byte Count Register
The early receive interrupt Receive Byte Count (RXBC) register is the 32-bit entity at offset 14h of
the CSR. This read only register reflects the value of the internal receive DMA byte count register.
Note: Unless the software uses a very complicated early receive interrupt scheme, which requires the use
of header RDFs, this register is of no value to software. Such a scheme could be used by software