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10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 117
Physical Layer Interface 7
Intel Fast Ethernet adapters all have a physical layer (PHY) component that interfaces the network
adapter to the wire. The MAC component of the adapter interfaces to the PHY component via the
IEEE Media Independent Interface (MII). Sometimes it is necessary for software to access these
PHY registers to properly configure the PHY. The Management Data Interface (MDI) in the 82557,
82558 and 82559 allows communication across the MII bus to registers on these PHYs.
For 100Mbps applications, the 82557 contains an IEEE MII compliant interface to the Intel 82555
physical layer device (or other MII compliant PHYs) which allow connections to both 10Mbps and
100Mbps networks. The 82558 and 82559 contain an embedded 82555 module. Software still
communicates with the embedded 82558 through the MDI port. The MDI register sets for several
different PHYs, including the 82555, are included in Section 7.2, “MDI Register Set” on the
Physical Layer Interface.
PRO/100B adapters use both Intel (and third-party) PHYs that support 10BASE-T, 100BASE-TX,
and/or 100BASE-T4 physical layers and are capable of auto-negotiation. The PHY module on the
PRO/100B adapter is a separate discreet component from the 82557. There are different versions
and generations of the PRO/100B that use different PHYs. Because certain vendor-specific
programming hooks may be required to fully support various PHYs, software should determine at
runtime which specific PHY is on the PRO/100B adapter being driven (Section 8.1.2, “PHY
Detection and Initialization” contains more details).
PRO/100+ adapters use the 82558’s embedded 82555, which supports auto-negotiation, 10BASE-
T, and 100BASE-TX. The 82559 also contains an embedded 82555. Although the PHY is
embedded in the 82558 and 82559, software still accesses the PHY via the MDI interface in the
manner that software uses on 82557 based adapters.
This section includes information on MDI, the 82555 MDI register sets, and auto-negotiation (N-
Way) functionality. It also includes information for items specific to working with the 82555 TX
PHY as well as the 82558 and 82559 embedded PHYs.
7.1 Management Data Interface (MDI)
The 82553, 82555, and other MII compliant devices provide status and accept management
information via the Management Data Interface (MDI). This is accomplished via read and write
operations to various registers according to the IEEE 802.3u MII specification. A read or write of a
particular register is called a management frame, which is sent serially over the MDIO pin
synchronous to MDC. Read and Write cycles are from the perspective of the controller. Therefore,
the controller would always drive the Start, Opcode, PHY Address and Register Address on to the
MDIO pin. For a write, the controller would also drive the transition bits and the data. For a read,
the PHY drives the transition bits and data onto the MDIO pin. The controller should drive address
and data on the falling edge of MDC and the PHY latches that data on the rising edge of MDC. In
an application where only one PHY is present, the PHY uses a default PHY address of 00001b. The
management frame structure is as follows: