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44 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Host Software Interface
6.3.3.1 PORT Software Reset
The Port Software Reset is synonymous with the software reset and is used to issue a complete
reset to the device. Software must wait for ten system clocks and five transmit clocks before
accessing the SCB registers again. (This may be a conservative 10 µs delay loop in software.) A
software reset clears the device CSR and the PCI master block internal registers. It also requires the
device to be completely re-initialized.
6.3.3.2 PORT Self-test
The controller self-test begins by issuing an internal selective reset and running a general internal
self-test of the device. The self-test function can be used to test the device micromachine
functionality, internal registers and internal ROM. After the self-test is completed, the results are
written to memory. The device provides the results of the self-test at the address specified by the
self-test port command. The format of the self-test results is shown in Figure 11. The self-test
command checks the following blocks:
• ROM. The contents of the entire ROM are sequentially read into a Linear Feedback Shift
Register (LFSR). The LFSR compresses the data and produces a signature unique to one set of
data. The results of the LFSR are then compared to a known good ROM signature. The pass or
fail result and the LFSR contents are written into the address specified by the self-test port
command.
• Parallel Registers: The micromachine performs write and read operations to all internal
parallel registers and checks the contents for proper values. The pass or fail result is then
written into the address specified by the self-test port command.
• Diagnose: The micromachine issues an internal diagnose command to the serial subsystem.
The pass or fail result of the diagnose command is written into the address specified by the
self-test port command.
where
S (bit 12) General Self Test result: 0 = pass, 1 = fail
D (bit 5) Diagnose result: 0 = pass, 1 = fail
M (bit 3) Register result: 0 = pass, 1 = fail
R (bit 2) ROM Content result: 0 = pass, 1 = fail
After completing the self-test and writing the results to memory, the device executes a full internal
reset and re-initializes to the default configuration.
Figure 11. Self-Test Results Format
Odd Word Even Word
31 16 15 0
CROM Content Signature
0 00 00 00 00 00 00 00 00 00 S0 00 00 0D 0M R0 0