Filter
Top Products
88 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Host Software Interface
While the CU pre-fetches the address and byte count of one buffer, the transmit DMA is
transferring the previous buffer to the transmit byte machine. Completion of a buffer transfer by the
transmit DMA triggers the CU to initiate the transmit DMA for the next buffer (if it is already pre-
fetched) and to start the pre-fetch of the next buffer. The buffer pre-fetch cycle is terminated when
the transmit DMA reads the last buffer (indicated by the TBD number) and transfers it to the
transmit FIFO.
Internally, the controller CU performs the following sequence during transmission:
1. Begins execution of the transmit action command.
2. Reads and saves the TBD array address.
3. If the TCB size field is greater than zero, the device performs as follows:
a. If the TBD array address is not equal to all ones, the CU performs a pre-fetch and transfer
cycle, initiates the transmit DMA to the address of the first byte of the destination address
field in the CB and to the byte count of the last specified data byte in the command block.
b. If the TBD array address equals all ones, after completing DMA of the command block
the CU writes the end of command byte to the transmit FIFO.
4. If the TCB size field in the command block is zero, it runs a buffer pre-fetch and transfer cycle
and forces one dummy DMA completion.
5. The CU waits for completion of the transmit command. This includes only the transfer of the
whole frame to the transmit FIFO subsystem, not the frame transmission by the CSMA/CD
unit. At this point, the device posts the C bit (to 1) in the TCB. The CPU can reclaim the TCB
and associated data structures.
6. If transmission completed with a collision (but did not exceed the maximum collisions),
regardless of errors, the subsystem generates a re-transmit command and sends the data bytes
again from the FIFO. This causes re-transmission of the frame without any additional PCI bus
access.
7. If the transmit DMA encountered an underrun due to a lack of PCI bus bandwidth, it appends a
jam pattern to the end of the partially transmitted frame. Frames that are aborted during
transmission are jammed. Such an interruption of transmission can be caused by several
different events. Jamming will not start before completion of pre-amble transmission (before
the first byte of the destination address is sent). Collisions detected during transmission of the
last 11 bits of the frame will not result in jamming.
8. The device CU completes the transmit action command.
The device may report completion of a transmit command before the actual transmission on the
link has completed. Software can reuse the resources to prepare a new transmit command. When
the frame is eventually transmitted on the link, the CSMA/CD sub-system will return the status of
the transmission to the 82557 micro-machine, but the TxCB Status WILL NOT be updated in host
memory. The CU will update the internal Tx counters according to the Tx status
6.4.2.5.3 Framing Operation
The transmit byte machine maintains the following registers for construction of frames: pre-amble
pattern, SFD field, source address, CRC generator, and jam patterns.
After the transmit byte machine reads the transmit command from the transmit FIFO, a frame is
constructed and transferred to the transmit bit machine for bit and nibble transmission. The
transmit byte machine performs the following sequence:
1. Pre-amble bytes are transferred according to pre-amble length configuration parameter.