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82555 10/100 Mbps LAN Physical Layer
Interface
Networking Silicon
Datasheet
Product Features
■
Optimal integration for lower cost solutions
—Integrated 10/100 Mbps single chip
physical layer interface solution
—Complete 10/100 Mbps MII compliance
with MDI support
—Full duplex operation in 10 Mbps and
100 Mbps modes
—IEEE 802.3u Auto-Negotiation support
for 10BASE-T half and full duplex,
100BASE-TX half and full duplex, and
100BASE-T4 configurations
—Parallel detection algorithm for legacy
support of non-Auto-Negotiation
enabled link partner
—Integrated 10BASE-T transceiver with
built in transmit and receive filters
—Glueless interface to T4-PHY for
combination TX/T4 designs with single
magnetics
—Glueless support for 4 LEDs: activity,
link, speed, and duplex
—LED function mapping support via MDI
—Low external component count
—Single 25 MHz clock support for 10
Mbps and 100 Mbps (crystal or
oscillator)
—Single magnetics for 10 Mbps and 100
Mbps operation
—QFP 100-pin package
■
Performance enhancements
—Flow control support for IEEE 802.3x
Auto-Negotiation and Bay Technologies
PHY Base* scheme
—Adaptive Channel Equalizer for greater
functionality over varying cable lengths
—High tolerance to extreme noise
conditions
—Very low emissions
—Jabber control circuitry to prevent data
loss in 10 Mbps operation
—Auto-polarity correction for 10BASE-T
—Software compatible with 82557 drivers
■
Repeater functionality
—Repeater mode operation
—Support for forced speed of 10 Mbps
and 100 Mbps
—Automatic carrier disconnect for IEEE
802.3u compliance
—Auto-Negotiation enable/disable
capability
—Receive port enable function
—Support for 32 configurable addresses
—Narrow analog side (14 mm) for tight
packing in repeater and switch designs
Document Number: 666252-004
Revision 2.0
March 1998
Notice:
Notice: