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14 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
PCI Interface
4.1.6 Class Code (Offset 9)
The class code, 020000h, identifies the device as an Ethernet adapter.
4.1.7 Cache Line Size (Offset C)
This register specifies the system cache line size in units of 32-bit words and can be read or written
to. The system BIOS or OS should initialize this register at power on or after a PCI reset.
The 82557 does not support Memory Write and Invalidate (MWI) and therefore returns 0 when this
register is read. The 82258 and 82559 support the MW I command and must support this register.
The 82558 and 82559 can only support cache line sizes of 8 and 16 Dwords. Any value other than
8 or 16 written to the register is ignored, and the device does not use the MWI command. If a value
other than 8 or 16 is written into the Cache Line Size (CLS) register, the device returns all zeroes
when the CLS register is read.
Bit 3 is set to 1 only if the value 00001000b (8) is written to this register. Bit 4 is set to 1 only if the
value 00010000b (16) is written to this register. All other bits are read only and will return 0 on
read.
4.1.8 Latency Timer (Offset D)
This register specifies, in units of PCI bus clocks, the minimum time that a bus master can retain
ownership of the bus. This value is set by the PCI bus arbitrator based on the values in the
maximum latency (Max_Lat) and Maximum Grant (Max_Gnt) registers.
4.1.9 Header Type (Offset E)
This byte field identifies the layout of the second part of the predefined configuration space header
and if the device is a multi-function component. The 82557 and 82558 are both single function
devices and have this register hard-coded to 00h. For the 82559, the value of this register is
determined by a bit in the EEPROM. This register should read 00h for a standard Ethernet adapter,
00h.
82559ER A-Step 09h 2.2 Yes
82550 0Ch, 0Dh, 0Eh 2.2 Yes
82551 0Fh, 10h 2.2 Yes
Table 2. Device and Revision ID
Device Revision ID
PCI Revision
Supported
Intel Driver
Supported
Figure 4. Cache Line Size
76543210
000RWRW000