Filter
Top Products
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 53
Host Software Interface
words before the end of the frame. If the Type/Length field contains a Type value, the device does
not generate an early interrupt, except in the case where the Type value is 8137h (IPX) or 0800h
(IP) and the device is configured to generate early interrupts on IPX or IP frames. In these two
cases, it is known that the actual frame length is defined in bytes 17 and 18.
The early receive interrupt value X, in 8 bytes resolution, is programmed into the Early Rx Int
register at address 18h in the device’s CSR. When this value is all zeros no early interrupt is
generated. The Early interrupt is indicated by the ER bit in the SCB. and the assertion of INTA#. X
should be determined by the driver as a function of the interrupt latency, PCI speed, etc.
The device also generates an interrupt at the end of the frame that will assure that no frame is
missed (in case of a race condition), but is in most cases ignored by software (the interrupt is either
already asserted or masked since the driver is in the Interrupt Handler).
The following list describes special cases for early receive interrupt assertion:
• If the programmed value is larger than the frame length, the device asserts the interrupt when it
is ready to post the length field into memory.
• Short and overrun frames that contain less than the length minus the programmed value do not
generate an early interrupt.
• The device does reclaim the RFD used by a frame that caused an early interrupt if this frame is
an error frame and the device is configured to discard bad frames. This implies that the
assertion of an ER interrupt does not guarantee that this frame will also generate an FR
interrupt (in other words, the driver should not poll for the end of frame if it is not set). If the
device is configured to SBF no RFD is reclaimed and the driver may safely assume that an FR
interrupt and RFD status will follow the ER interrupt.
• The ER interrupt mechanism operates only if the device does not discard the incoming frames.
Therefore, the device does not generate ER interrupts before the RU is started. The device also
may not assert the ER interrupt for frames that exceed the allocated buffer space and are being
discarded.
• When the ER interrupt mechanism is first activated, it may not generate an ER interrupt for the
first frame. An FR interrupt is generated if the RU is ready.
6.3.8 Flow Control Register
The flow control register is a 16-bit field at offset 18h (bits 23:8) of the CSR. This register does not
exits on the 82557. It reflects flow control status information and contains some control bits that
allow software to alter the flow control configuration parameters of the device.
Table 29. Flow Control Registers Location
Upper Word (D31:D16) Lower Word (D15:D0) Offset
SCB Command Word SCB Status Word Base + 0h
SCB General Pointer Base + 4h
PORT Base + 8h
EEPROM Control Register Reserved Base + Ch
MDI Control Register Base + 10h
Early Receive Interrupt Receive Byte Count Register Base + 14h
PMDR FC Xon/Xoff FC Threshold Early Rx Int Base + 18h