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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 23
PCI Interface
device may start the next cycle using either MW or MWI according to the conditions listed above.
If the PCI latency timer or the 82558 (or later generation device) arbitration counter expires during
a MWI cycle, the device continues the cycle until the end of the cache line.
If the device started a MW cycle and reaches a cache line boundary, it either terminates the cycle or
continues according to the Term on CL configuration bit (Section 6.4.2.3, “Configure (010b)”). If
the Term on CL bit is set, the device terminates the MW cycle and attempts to start a new cycle.
The new cycle is a MWI cycle if all conditions are met. If the bit is not set, the device continues the
MW cycle across the cache line boundary if required.
4.2.2 Read Align
The Read Align feature is aimed to enhance performance in cache line oriented systems. Starting a
PCI transaction in these systems on a non-cache line aligned address may result in low
performance.
To solve this performance problem, the controller can be configured to terminate Transmit DMA
cycles on a cache line boundary, and start the next transaction on a cache line aligned address. This
feature is enabled when the Read Align Enable bit is set in device Configure command
(Section 6.4.2.3, “Configure (010b)”).
If this bit is set, the device operates as follows:
• When the device is close to running out of resources on the Transmit DMA (in other words,
the Transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest
cache line boundary when possible.
• When the arbitration counters feature is enabled (maximum Transmit DMA byte count value is
set in configuration space), the device switches to other pending DMAs on cache line
boundary only.
4.2.3 Odd Byte Alignment Support
Various data structures have special memory alignment requirements. These alignment
requirements are detailed in Section 6.2.1, “LAN Controller Addressing Format”.