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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 89
Host Software Interface
2. The SFD field is transferred.
3. Start CRC calculation.
4. Read and transfer the 6 destination address bytes from the transmit FIFO.
5. If the no source address insertion configuration parameter is zero, the individual address
should be transferred as the source address. Otherwise, the source address should be read and
transferred from the transmit FIFO. If the no source address insertion is 1 and there are less
than address length bytes in the transmit FIFO, a DMA underrun is forced.
6. All remaining bytes from the transmit FIFO are read and transferred. These are the length and
data fields.
7. The CRC is transferred.
8. If the device is configured to enable padding, the flag bytes (07Eh) are transferred
automatically so that a valid frame (64 bytes including CRC) is transferred onto the link.
If a collision or underrun occurred during transmission, the transmit byte machine completes the
transfer of the pre-amble and transfers 4 bytes of the jam pattern. If a collision occurred, the retry
counter is incremented. Jamming will not start before completing pre-amble transmission.
If a collision is detected during transmission of the last 11 bits in the frame, it does not result in
jamming. If the collision is detected during transmission of the last bit or later, the collision is not
reported and re-transmission does not occur. This can happen for an invalid frame shorter in length
than the slot time.
Note: A DMA underrun cannot logically occur during the pre-amble because the serial subsystem
generates its own pre-amble.
6.4.2.5.4 Delayed CNA Interrupts
The 82558 and later generation controllers have the ability to delay the CNA interrupt for a
predefined length of time, called the CNA interrupt delay (CID). If the CID is set to a non-zero
value, the device does not assert the interrupt immediately when entering a non-active state.
Instead, it initializes an internal counter with the CID parameter. The interrupt is asserted only
when the counter expires. If a CU resume or CU start command is issued while the counter is
counting, the interrupt will not be asserted. This opens a window for the device driver to set a new
command without the overhead of an additional interrupt service routine (ISR).
The device delays the interrupt, regardless of whether it is configured for CI interrupts or CNA
interrupts. However, the controller does not delay the updating of the CU status field. Therefore, if
the CID is greater than zero, it posts the CU status field (without the CNA bit) before it posts the
CNA bit and asserts the INTA# signal. (This feature is primarily targeted to NDIS systems but can
be beneficial for other systems as well.)
The CID parameter is set on a frame by frame basis, and its value is read by the device from the
TCB. Since the internal counter is automatically initialized to the CID value from the current TCB,
the existing value of the counter (set by the previous TCB) is overwritten, causing the counter to
reset even if it has not yet reached zero. This allows a rolling delay, where a number of back to
back TCBs can be given to the controller while only generating one interrupt at the end of the
chain.
The purpose of the delay is to avoid issuing this interrupt if it is not required. It is assumed that the
interrupt is not required in the following cases:
• The device was issued another action command and the CU returns to the active state.