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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual v
Contents
7.3.6 100BASE-TX Receive Error Frame Counter: Register 21...................................127
7.3.7 Receive Symbol Error Counter: Register 22........................................................127
7.3.8 100BASE-TX Receive EOF Error Counter: Register 23......................................127
7.3.9 10BASE-T Receive EOF Error Counter: Register 24 ..........................................127
7.3.10 10BASE-T Transmit Jabber Detect Counter: Register 25 ...................................127
7.3.11 Equalizer Control and Status Register: Register 26 ............................................128
7.3.12 Special Control Register: Register 27..................................................................129
7.4 Auto-Negotiation Functionality..........................................................................................130
7.4.1 Description...........................................................................................................130
7.4.2 Parallel Detection.................................................................................................131
7.5 Vendor-Specific PHY Programming .................................................................................132
7.5.1 Intel 82555 TX PHY .............................................................................................132
7.5.2 82558 and 82559 Embedded PHY Unit...............................................................132
8 Programming Recommendations............................................................................................135
8.1 Adapter Initialization .........................................................................................................135
8.1.1 8255x Initialization ...............................................................................................135
8.1.2 PHY Detection and Initialization ..........................................................................135
8.1.3 NOS Specific Initialization....................................................................................136
8.2 Transmit Processing .........................................................................................................136
8.3 Frame Reception ..............................................................................................................136
8.4 Interrupt Processing..........................................................................................................137
Appendices
A Wake-up Functionality ..............................................................................................................139
B 82550 and 82551QM Specific Information...............................................................................155
Figures
1 82557 Network Interface Card Block Diagram .............................................................................5
2 Command Register.....................................................................................................................12
3 Command Register.....................................................................................................................13
4 Cache Line Size..........................................................................................................................14
5 Base Address Register for Memory Mapping .............................................................................15
6 Base Address Register for I/O Mapping .....................................................................................15
7 Expansion ROM Base Address Register....................................................................................17
8 8255x Memory Architecture........................................................................................................28
9 SCB Status Word........................................................................................................................34
10 SCB Command Word .................................................................................................................36
11 Self-Test Results Format............................................................................................................44
12 EEPROM Control Register .........................................................................................................46
13 EEPROM Read Timing Diagram ................................................................................................48
14 General Action Command Format ..............................................................................................58
15 NOP Command Format ..............................................................................................................59
16 Individual Address Setup Command Format..............................................................................60
17 Configure Command Format ......................................................................................................62
18 Multicast Setup Command Format .............................................................................................82
19 Transmit Command Format........................................................................................................83