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iv Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Contents
5 EEPROM Interface....................................................................................................................... 25
6 Host Software Interface .............................................................................................................. 27
6.1 The Shared Memory Architecture.......................................................................................27
6.2 Initializing the LAN Controller .............................................................................................29
6.2.1 LAN Controller Addressing Format........................................................................29
6.3 Controlling the Device......................................................................................................... 31
6.3.1 Control / Status Registers (CSR)........................................................................... 31
6.3.2 System Control Block (SCB).................................................................................. 33
6.3.3 PORT Interface......................................................................................................43
6.3.4 EEPROM Control Register .................................................................................... 45
6.3.5 Management Data Interface Control Register ....................................................... 49
6.3.6 Receive Byte Count Register................................................................................. 51
6.3.7 Early Receive Interrupt .......................................................................................... 52
6.3.8 Flow Control Register ............................................................................................53
6.3.9 Power Management Driver Register...................................................................... 54
6.3.10 General Control Register.......................................................................................56
6.3.11 General Status Register ........................................................................................ 56
6.4 Shared Memory Structures.................................................................................................57
6.4.1 Action Commands and Operating Modes..............................................................57
6.4.2 Specific Action Commands....................................................................................59
6.4.3 Receive Operation ................................................................................................. 99
6.5 Command Unit and Receive Unit Operation.....................................................................105
6.5.1 Starting and Completing Control Commands ......................................................105
6.5.2 Generating and Acknowledging Interrupts...........................................................105
6.5.3 Command Unit Control ........................................................................................106
6.5.4 Receive Unit Control............................................................................................ 108
6.5.5 Updating SCB Status........................................................................................... 110
6.6 Flow Control......................................................................................................................110
6.6.1 PHY Based Flow Control.....................................................................................111
6.6.2 Frame Based Flow Control..................................................................................111
6.6.3 Priority Aware Frame Based Flow Control...........................................................115
6.6.4 Half Duplex Flow Control..................................................................................... 116
6.7 Collision Backoff Modification in Switched Environments.................................................116
7 Physical Layer Interface ...........................................................................................................117
7.1 Management Data Interface (MDI) ...................................................................................117
7.2 MDI Register Set ..............................................................................................................118
7.2.1 Control Register: Register 0 ................................................................................119
7.2.2 Status Register: Register 1..................................................................................120
7.2.3 Identification Registers: Registers 2 and 3 ..........................................................121
7.2.4 Auto-Negotiation Advertisement Register: Register 4 .........................................122
7.2.5 Auto-Negotiation Link Partner Ability Register: Register 5 .................................. 122
7.2.6 Auto-Negotiation Expansion Register: Register 6 ...............................................123
7.3 Intel 82555 Specific Registers ..........................................................................................124
7.3.1 Status and Control Register: Register 16 ............................................................ 124
7.3.2 Special Control Register: Register 17..................................................................125
7.3.3 Clock Synthesis Test and Control Register: Register 18.....................................126
7.3.4 100BASE-TX Receive False Carrier Counter: Register 19 .................................126
7.3.5 100Base-TX Receive Disconnect Counter: Register 20...................................... 126