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33. Watchdog Timer
When the emulator is connected to operate the watchdog timer (WDT) during using the
H8S/2377F and H8S/2367F, the WDT continues operation during a break.
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When a counter value overflows during a break in the watchdog timer mode:
An internal reset signal is generated when the internal LSI is reset.
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When a counter value overflows during a break in the interval timer mode:
An interrupt request is generated, but it is suspended during a break.