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Rev.1.02 Jul 01, 2005 page 109 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 12. Timers
Under development
This document is under development and its contents are subject to change.
Item Specification
Count Source • External signals input to TBiIN pin (effective edge can be selected in program)
• Timer Bj overflow or underflow
Count Operation • Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide Ratio 1/(n+1) n: set value of the TBi register 0000h to FFFFh
Count Start Condition Set TBiS bit
(1)
to “1” (start counting)
Count Stop Condition Set TBiS bit to “0” (stop counting)
Interrupt Request Generation Timing
Timer underflow
TBiIN Pin Function Count source input
Read from Timer Count value can be read by reading the TBi register
Write to Timer • When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 12.7 lists specifications in event counter mode. Figure 12.19 shows TBiMR register in
event counter mode.
Table 12.7 Specifications in Event Counter Mode
Figure 12.19 TB0MR to TB5MR Registers in Event Counter Mode
Timer Bi Mode Register (i= 0 to 5)
Symbol
Bit Name FunctionBit Symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation Mode Select Bit
0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0
Count Polarity Select
Bit
(1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0 :
Counts falling edge of external signal
0 1 :
Counts rising edge of external signal
1 0 : Counts falling and rising edges of
external signal
1 1 : Do not set a value
b3 b2
NOTES:
1.Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can
be set to "0" or "1".
2.The port direction bit for the TBiIN pin must be set to "0" (input mode).
Has no effect in event counter mode.
Can be set to "0" or "1".
Event Clock Select Bit
0 : Input from TBiIN pin
(2)
1 : TBj overflow or underflow
(j = i
—
1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
RW
RW
RW
RW
-
RW
RW
RO
TB0MR, TB3MR registers
Set to "0" in event counter mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
When write in event counter mode, set to "0".
When read in event counter mode, its content is indeterminate.
After Reset
TB0MR to TB2MR 00XX0000b
TB3MR to TB5MR 00XX0000b
Address
039Bh to 039Dh
01DBh to 01DDh
i = 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.