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Rev.1.02 Jul 01, 2005 page 246 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 20. Flash Memory Version
Under development
This document is under development and its contents are subject to change.
20.3.4.9 Writing Command and Data
Write commands and data to even addresses in the user ROM area.
20.3.4.10 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to “0” (CPU rewrite mode disabled)
before executing the WAIT instruction.
20.3.4.11 Stop Mode
When entering stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10
bit to “1” (stop mode).
• Execute the instruction to set the CM10 bit to “1” (stop mode) and then the JMP.B instruction.
Example program BSET 0, CM1 ; Stop mode
JMP.B L1
L1:
Program after exiting stop mode
20.3.4.12 Low Power Dissipation Mode and On-chip Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program software command
• Read lock bit status