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Rev.1.02 Jul 01, 2005 page 147 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
14.1.2.2 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i = 0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i = 0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “001b”, “101b”, “110b”.
(3) “1” (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
14.1.2.3 LSB First/MSB First Select Function
As shown in Figure 14.19, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8-bit long.
Figure 14.19 Transfer Format
NOTE:
1. This applies to the case where the register bits are set as follows:
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock)
UiLCH bit in UiC1 register = 0 (no reverse)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
(2) When the UFORM bit = 1 (MSB first)
D1 D2 D3 D4 D5 D6 SPD0
D1 D2 D3 D4 D5 D6 SPD0
TXDi
RXDi
CLKi
D6 D5 D4 D3 D2 D1 D0
D7
TXDi
RXDi
CLKi
ST
ST
D7 P
D7 P
SP
SP
ST
ST
P
P
D6 D5 D4 D3 D2 D1 D0
D7
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit