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Rev.1.02 Jul 01, 2005 page 164 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
14.1.5 Special Mode 3 (IE Mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 14.16 lists the registers used in IE mode and the register values set. Figure 14.31 shows the
functions of bus collision detect function related bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR06 and IFSR07 bits in the IFSR0 register to enable the UART0/UART1 bus collision detect function.
Table 14.16 Registers to Be Used and Settings in IE Mode
Register Bit Function
UiTB 0 to 8 Set transmission data
UiRB
(1)
0 to 8 Reception data can be read
OER,FER,PER,SUM Error flag
UiBRG 0 to 7 Set a transfer rate
UiMR SMD2 to SMD0 Set to “110b”
CKDIR Select the internal clock or external clock
STPS Set to “0”
PRY Invalid because the PRYE bit = 0
PRYE Set to “0”
IOPOL Select the TXD/RXD input/output polarity
UiC0 CLK1, CLK0 Select the count source for the UiBRG register
CRS Invalid because the CRD bit = 1
TXEPT Transmit register empty flag
CRD Set to “1”
NCH Select TXDi pin output mode
CKPOL Set to “0”
UFORM Set to “0”
UiC1 TE Set this bit to “1” to enable transmission
TI Transmit buffer empty flag
RE Set this bit to “1” to enable reception
RI Reception complete flag
U2IRS
(2)
Select the source of UART2 transmit interrupt
U2RRM
(2)
, Set to “0”
UiLCH, UiERE
UiSMR 0 to 3, 7 Set to “0”
ABSCS Select the sampling timing at which to detect a bus collision
ACSE Set this bit to “1” to use the auto clear function of transmit enable bit
SSS Select the transmit start condition
UiSMR2 0 to 7 Set to “0”
UiSMR3 0 to 7 Set to “0”
UiSMR4 0 to 7 Set to “0”
IFSR0 IFSR06, IFSR07 Set to “1”
UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM Set to “0”
CLKMD0 Invalid because the CLKMD1 bit = 0
CLKMD1, RCSP, 7 Set to “0”
i= 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.