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Rev.1.02 Jul 01, 2005 page 222 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 18. CAN Module
Under development
This document is under development and its contents are subject to change.
18.16 CAN Interrupt
The CAN module provides the following CAN interrupts.
• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN0 Error Interrupt: Error Passive State
Error BusOff State
Bus Error (this feature can be disabled separately)
• CAN0 Wake-up Interrupt
When the CPU detects the CAN0 successful reception/transmission interrupt request, the MBOX bit in the
C0STR register must be read to determine which slot has generated the interrupt request.