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7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 43
7.2.1 CPU Clock and BCLK ........................................................................................................................ 43
7.2.2 Peripheral Function Clock ..................................................................................................................43
7.3 Clock Output Function ...............................................................................................................................43
7.4 Power Control ............................................................................................................................................44
7.4.1 Normal Operation Mode.....................................................................................................................44
7.4.2 Wait Mode .......................................................................................................................................... 46
7.4.3 Stop Mode..........................................................................................................................................48
7.5 Oscillation Stop and Re-oscillation Detection Function ............................................................................. 53
7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) .................................................... 53
7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ........................ 53
7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function ..................................................54
8. Protection ............................................................................................................................ 55
9. Interrupt ............................................................................................................................... 56
9.1 Type of Interrupts .......................................................................................................................................56
9.2 Software Interrupts .....................................................................................................................................57
9.2.1 Undefined Instruction Interrupt...........................................................................................................57
9.2.2 Overflow Interrupt ..............................................................................................................................57
9.2.3 BRK Interrupt .....................................................................................................................................57
9.2.4 INT Instruction Interrupt ..................................................................................................................... 57
9.3 Hardware Interrupts ...................................................................................................................................58
9.3.1 Special Interrupts ............................................................................................................................... 58
9.3.2 Peripheral Function Interrupts............................................................................................................58
9.4 Interrupts and Interrupt Vector ...................................................................................................................59
9.4.1 Fixed Vector Tables............................................................................................................................59
9.4.2 Relocatable Vector Tables .................................................................................................................59
9.5 Interrupt Control .........................................................................................................................................61
9.5.1 I Flag .................................................................................................................................................. 63
9.5.2 IR Bit ..................................................................................................................................................63
9.5.3 ILVL2 to ILVL0 Bits and IPL ............................................................................................................... 63
9.5.4 Interrupt Sequence ............................................................................................................................64
9.5.5 Interrupt Response Time.................................................................................................................... 65
9.5.6 Variation of IPL when Interrupt Request is Accepted ......................................................................... 65
9.5.7 Saving Registers ................................................................................................................................66
9.5.8 Returning from an Interrupt Routine ..................................................................................................67
9.5.9 Interrupt Priority .................................................................................................................................67
9.5.10 Interrupt Priority Resolution Circuit .................................................................................................. 67
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9.6 INT Interrupt ...............................................................................................................................................69
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9.7 NMI Interrupt .............................................................................................................................................. 73
9.8 Key Input Interrupt .....................................................................................................................................73
9.9 CAN0 Wake-up Interrupt ............................................................................................................................73
9.10 Address Match Interrupt ...........................................................................................................................74
10. Watchdog Timer ................................................................................................................ 76
10.1 Count Source Protective Mode ................................................................................................................ 77