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Rev.1.02 Jul 01, 2005 page 134 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 14. Serial I/O
Under development
This document is under development and its contents are subject to change.
14.1.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists
the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock
synchronous serial I/O mode and the register values set.
Table 14.1 Clock Synchronous Serial I/O Mode Specifications
Item Specification
Transfer Data Format Transfer data length: 8 bits
Transfer Clock The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
• fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
The CKDIR bit = 1 (external clock) : Input from CLKi pin
Transmission, Reception Control
_______ _______ _______ _______
Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission Start Condition Before transmission can start, the following requirements must be met
(1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
_______ _______
• If CTS function is selected, input on the CTSi pin = L
Reception Start Condition Before reception can start, the following requirements must be met
(1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Interrupt Request For transmission, one of the following conditions can be selected
Generation Timing • The UiIRS bit
(2)
= 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error Detection Overrun error
(3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select Function • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS0 and RTS0 are input/output from separate pins
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. The U0IRS and U1IRS bits respectively are bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.
3. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not
change.