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Spinpoint M8U-Internal Product Manual REV 3.4
24
INSTALLATION
5.2 Drive Electronics
The Spinpoint M8U hard disk drive attains its intelligence and performance through the specialized
electronic components mounted on the PCBA. The components are mounted on one side of the PCBA.
The Preamplifier IC is the only electrical component that is not on the PCBA. It is mounted on the flexible
circuit inside the HDA. Locating the Preamplifier IC as close as possible to the read/write heads via surface
mount technology improves the signal to noise ratio.
5.2.1 Digital Signal Process and Interface Controller
The DSP core controller has a dual ARM CPU that incorporates a true 16-bit digital signal processor (DSP),
a bus controller unit (BCU), an interrupt controller unit (ICU), a general purpose timer (GPT), and SRAM
5.2.2 USB Interface Controller
The USB interface disk controller works in conjunction with the DSP core to perform the USB interface
control, buffer data flow management, disk format/read/write control, and error correction functions of an
embedded disk drive controller. The DSP communicates with the disk controller module by reading from
and writing to its various internal registers.
To the DSP core, the registers of the disk controller appear as unique memory or I/O locations that are
randomly accessed and operated upon. By reading from and writing to the registers, the DSP core initiates
operations and examines the status of the different functional blocks. Once an operation is started, successful
completion or an error condition may cause the disk controller to interrupt the DSP core, which then
examines the status registers of the disk controller and determines an appropriate course of action. The local
DSP core may also poll the device to ascertain successful completion or error conditions.
5.2.2.1 The Host Interface Control Block
The HBI module responds to the command issued from the host and controls the data transfer between the
buffer memory module and the host.
The HBI module supports the following main features:
• Power Saving
• 8/16 bit host interface
• A deep FIFO (32 x 32 bit) used as the temporary buffer for the data transfer
• 512 byte
• Microprocessor Interrupts
• 6 endpoints ( EP0-EP2 IN/OUT)
• Mass Storage class bulk-only transport with flow control
• Support Control transport
• Support Suspend/resume mode