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Spinpoint M8U-Internal Product Manual REV 3.4
26
INSTALLATION
5.2.2.5 Power Management
Power management features are incorporated into each block of the Spinpoint M8U. This allows the
designer to tailor the amount of power management to the specified design. Other power management
features include:
• Independent power management control for each block.
• DSP block powered down and up when needed.
• Disk Sequencer and associated disk logic powered up when the Disk Sequencer is started.
• Weak pull-up structure on input pins to prevent undesirable power consumption due to floating CMOS
inputs.
5.2.3 Read/Write IC
The Read/Write IC, shown in Figure 5-3 provides read/write-processing functions for the drive. The
Read/Write IC receives the Read GATE and Write GATE signals, write data, and servo AGC and gates from
the Interface Controller. The Read/Write IC sends decoded read data and the read reference clock. It
receives write data from the Interface Controller.
The 88C9310 which is embedded in 88i9322(Rev2.0)is a sampled-data digital PRML channel designed to
work with a disk controller and a read/write preamplifier to provide the signal processing elements required
to build a state of the art high density, high speed disk drive. The 88C9310 implements a noise predictive,
PRML Viterbi read channel (supporting) zone-bit recording,
The read/write channel functions include a time base generator, AGC circuitry, asymmetry correction
circuitry (ASC), analog anti-aliasing low-pass filter, analog to digital converter (ADC), digital FIR filter,
timing recovery circuits, Viterbi detector, sync mark detection, 30/32 rate block code ENDEC, serializer and
de-serializer, and write pre-compensation circuits. Servo functions include servo data detection and PES
demodulation. Additionally the 88C9310 contains specialized circuitry to perform various parametric
measurements on the processed read signal. This allows for implementation of self-tuning and optimization
capability in every
drive built using the 88C9310.
A 10-bit NRZ interface is provided to support high speed data transfers and from the controller.
Programming of the 88C9310 is performed through a serial interface. The serial interface is also used to
read various channel parameters that are computed on the fly.
5.2.3.1 Time Base Generator
The time base generator provides the write frequency and serves as a reference clock to the
synchronizer during non-read mode.
5.2.3.2 Automatic Gain Control
The AGC accepts a differential signal from the pre-amp, and provide a constant output
amplitude to the analog filter. It’s capable of accepting signal ranges from 50 mV to 400 mVppd.
5.2.3.3 Asymmetry Correction Circuitry (ASC)
The ASC circuit is designed to correct for amplitude asymmetry introduced by MR heads. The
compensation range of this circuit is +/-25%. This circuit allows optimal bias current to be used
independent of the asymmetry effect.