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Spinpoint M8U-Internal Product Manual REV 3.4
43
INSTALLATION
When a transceiver operating in high-speed mode transmits, the transmit current is directed into either the D+
or D- data line. A J is asserted by directing the current to the D+ line, a K by directing it to the D- line.
When each of the data lines is terminated with a 45Ω resistor to the device ground, the effective load
resistance on each side is 22.5Ω. Therefore, the line into which the drive current is being directed rises to
17.78 ma * 22.5Ω or 400 mV (nominal). The other line remains at the device ground voltage. When the
current is directed to the opposite line, these voltages are reversed.
6.2.2.4 High-speed (480Mb/s) Signaling Rise and Fall Times
The transition time of a high-speed driver must not be less than the specified minimum allowable differential
rise and fall time (T
HSR and THSF). Transition times are measured when driving a reference load of 45Ω to
ground on D+ and D-.
For a hub, or for a device with detachable cable, the 10% to 90% high-speed differential rise and fall times
must be 500 ps or longer when measured at the A or B receptacles (respectively).
For a device with a captive cable assembly, it is a recommended design guideline that the 10% to 90% high
speed differential rise and fall times must be 500 ps or longer when measured at the point where the cable is
attached to the device circuit board.
6.2.2.5 High-speed (480Mb/s) Receiver Characteristics
As shown in Figure 6-11, a high-speed capable transceiver which is operating in high-speed mode “listens”
for an incoming serial data stream with the high-speed differential data receiver and the transmission
envelope detector. Additionally, a downstream facing high-speed capable transceiver monitors the amplitude
of the differential voltage on the lines with the disconnection envelope detector.
When receiving in high-speed mode, the differential receiver must be able to reliably receive signals that
conform to the Receiver Eye Pattern. Additionally, it is a strongly recommended guideline that a high-speed
receiver should be able to reliably receive such signals in the presence of a common mode voltage component
(V
HSCM) over the range of –50 mV to 500 mV (the nominal common mode component of high-speed
signaling is 200 mV). Low frequency chirp J and K signaling, which occurs during the Reset handshake,
should be reliably received with a common mode voltage range of –50 mV to 600 mV.
Reception of data is qualified by the output of the transmission envelope detector. The receiver must disable
data recovery when the signal falls below the high-speed squelch level (V
HSSQ) defined in Table 6-2.
(Detector must indicate squelch when the magnitude of the differential voltage envelope is ≤ 100 mV, and
must not indicate squelch if the amplitude of differential voltage envelope is ≥ 150 mV.) Squelch detection
must be done with a differential envelope detector, such as the one shown in Figure 6-10. The envelope
detector used to detect the squelch state must incorporate a filtering mechanism that prevents indication of
squelch during differential data crossovers.
The definition of a high-speed packet’s SYNC pattern, together with the requirements for high-speed hub
repeaters, guarantee that a receiver will see at least 12 bits of SYNC (KJKJKJKJKJKK) followed by the data
portion of the packet. This means that the combination of squelch response time, DLL lock time, and end of
SYNC detection must occur within 12 bit times. This is required to assure that the first bit of the packet
payload will be received correctly.
In the case of a downstream facing port, a high-speed capable transceiver must include a differential envelope
detector that indicates when the signal on the data exceeds the high-speed Disconnect level (V
HSDSC) as
defined in Table 6-2. (The detector must not indicate that the disconnection threshold has been exceeded if
the differential signal amplitude is ≤ 525 mV, and must indicate that the threshold has been exceeded if the
differential signal amplitude is ≥ 625 mV.)