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Spinpoint M8U-Internal Product Manual REV 3.4
25
INSTALLATION
5.2.2.2 The Buffer Control Block
The Buffer Control block manages the flow of data into and out of the buffer. Significant automation
allows buffer activity to take place automatically during read/write operations between the host and the disk.
This automation works together with automation within the Host Interface Control and Disk Control blocks
to provide more bandwidth for the local microprocessor to perform non-data flow functions.
The buffer control circuitry keeps track of buffer full and empty conditions and automatically works with the
Disk Control block to stop transfers to or from the disk when necessary. In addition, transfers to or from the
host are automatically stopped or started based on buffer full or empty status.
Additional functionality is provided in the Buffer Control block through the following features:
• Increased automation to support minimal latency read operations with minimal latency.
• Capability to support the execution of multiple consecutive Auto-Write commands without loss of data
due to overwriting of data.
• Auto write pointer.
• A disk sector counter that can monitor the transfers between the disk and buffer.
• Read/Write cache support.
5.2.2.3 The Disk Control Block
The Disk Control block manages the flow of data between the disk and the buffer. Many flexible features and
elements of automation have been incorporated to complement the automation contributed by the Host and
Buffer blocks.
The Disk Control block consists of the programmable sequencer (Disk Sequencer), CDR/data split logic, disk
FIFO, fault tolerant sync detect logic, and other support logic.
The programmable sequencer contains a 31-by-4 byte programmable SRAM and associated control logic,
which is programmed by the user to automatically control all single track format, read, and write operations.
From within the sequencer micro program, the Disk Control block can automatically deal with such real time
functions as defect skipping, servo burst data splitting, branching on critical buffer status and data compare
operations. Once the Disk Sequencer is started, it executes each word in logical order. At the completion of
the current instruction word, it either continues to the next instruction, continues to execute
some other
instruction based upon an internal or external condition having been met, or it stops.
During instruction execution or while stopped, registers can be accessed by the DSP to obtain status
information reflecting the Disk Sequencer operations taking place.
5.2.2.4 The Disk ECC Control Block
The Disk Control Block supports a programmable iterative Error Correction Code (ECC) that is capable of
achieving extremely low data failure rates. The iterative code is designed to replace the Reed-Solomon (RS)
codes and is designed to operate well in random noise as well as in a defect-dominated environment. RS-
ECC-less iterative decoder with programmable Noise Predictive non-linear Viterbi detector to accommodate
a large range of data densities