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104
Sundance Technology ST201 PRELIMINARY draft 2
byte 3 byte 2 byte 1 byte 0 Offset
FIGURE 12: ST201 PCI Register Layout
Reserved PowerMgmtCtrl 0x54
Reserved 0x60
Reserved 0x5c
Reserved 0x58
PowerMgmtCap NextItemPtr CapId 0x50
Reserved 0x4c
Reserved 0x48
Reserved 0x44
Reserved 0x40
MinGnt InterruptPin InterruptLine 0x3cMaxLat
Reserved 0x38
ExpRomBaseAddress 0x30
Reserved CapPtr 0x34
SubsystemId SubsystemVendorId 0x2c
Reserved 0x28
Reserved 0x24
Reserved 0x20
Reserved 0x1c
Reserved 0x18
MemBaseAddress 0x14
IoBaseAddress 0x10
HeaderType LatencyTimer CacheLineSize 0x0cReserved
ClassCode RevisionId 0x08
ConfigStatus ConfigCommand 0x04
DeviceId VendorId 0x00
0xe0..