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Sundance Technology ST201 PRELIMINARY draft 2
tion of the “first TFD” in the TxDMAList.
Restore the TxDMANextPtr of the “first TFD”,
and restart this process.
4. Copy the value of the “first TFD’s” TxDMANex-
tPtr into the TxDMANextPtr field of the inserted
TFD.
5. Update the TxDMANextPtr field of the “first
TFD” with the address of the inserted TFD.
TRANSMIT INTERRUPT OPTIMIZATIONS
The transmit mechanism can be optimized by the
host system, allowing a reduction in the number of
interrupts generated. The host system can limit the
number of frames in the TxDMAList for which a
TxDMAComplete interrupt is generated. For exam-
ple, the host system could only set TxDMAIndicate
for the frame on the tail of the list (clearing TxD-
MAIndicate for the current tail before adding a new
frame to the list). Or it might require an interrupt
every N frames. In any case, on each interrupt it
would then dequeue all of the frames which were
transferred via TxDMA before that interrupt
occurred (TFDs in which TxDMAComplete is set).
Obviously, the host system is responsible for the
trade-off between latency and the number of inter-
rupts generated by the ST201.
RXDMA SEQUENCE
The ST201 performs the following procedure dur-
ing transfers of RxDMA frames.
1. Verifies the RxDMAListPtr register is non-zero.
2. Verifies not in the RxDMAHalt state.
3. Resets the RxDMAStatus register.
4. Fetches ReceiveFrameStatus from the current
RFD. If the current RFD has the RxDMACom-
plete bit set, the ST201 performs an implicit
RxDMAHalt, halting the RxDMA process. (If
RxDMAPollPeriod contains a nonzero value,
the ST201 will then poll on the RxDMACom-
plete bit, waiting for it to be cleared before con-
tinuing.) Otherwise, the RxDMA process
continues.
5. Waits for the top receive frame to become eli-
gible for RxDMA.
6. Transfers the frame via RxDMA into the frag-
ments specified in the RFD, or into the implied
buffer if ImpliedBufferEnable is set. If there is
more data in the frame than space in the frag-
ment buffers, the ST201 generates a RxD-
MAOverflow error.
7. As the frame is being transferred by the
RxDMA process, the ST201 maintains the
RxDMAStatus register, specifically the RxD-
MAFrameLen field.
8. At the end of the frame RxDMA process, the
ST201 updates the RxDMAStatus register with
any error codes from the frame transfer and
sets the RxDMAComplete bit.
9. Issues an internal RxDiscard and waits for
completion.
10. If a RxDMAHalt has been asserted, waits until
a RxDMAResume has been issued.
11. Fetches RxDMANextPtr from the RFD. If RxD-
MANextPtr is zero and polling is enabled, the
ST201 begins a polling loop. If polling is dis-
abled, the ST201 loads the fetched value into
RxDMAListPtr.
12. Writes ReceiveFrameStatus to the RFD in host
memory.
13. If a polling loop has begun, polls on RxDMAN-
extPtr until a non-zero value is fetched. Loads
the value into RxDMAListPtr.
14. If the RxDMAListPtr value is zero (polling is
disabled), then the RxDMA Logic becomes
idle, waiting for a non-zero value to be written
into the RxDMAListPtr register.
15. Repeat process at step 1.
WAKE EVENT PROGRAMMING
This section describes the sequences involved in
programming ST201 for wake events.
Powering down the ST201 will typically occur while
in the operating state (D0). The host system is noti-
fied by the operating system that a power state
change is imminent. The host system prepares for
power down with these steps.
1. Halt the ST201 TxDMA process, halt the
TxDMA Logic, wait for any TxDMA in progress
to complete, wait for any transmissions to com-
plete, and issue TxReset to reset the TxFIFO
pointers.
2. Perform the RxDMA process for any receive
frames remaining in RxFIFO, halt RxDMA
Logic (frames will potentially keep filling the
RxFIFO between now and when operating sys-
tem powers down the system, and once the
power down state is entered and Wakeup
Packet scanning enabled, these frames in the
RxFIFO will be scanned and could potentially
wake the system immediately).
3. Clear IntEnable register so no interrupts occur
before PowerState is changed.
4. Save any volatile state, such as a pending
power state and the HashTable settings, to
system memory (system memory is restored
after a power down).
5. The host system transfers Wakeup Packet pat-
terns to the TxFIFO (if Wakeup Packets are to
be enabled) and programs the WakeEvent reg-
ister to enable the desired wake events. The