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A-10
(RESYNCHRONIZE JTAG)) and before C-SPY has regained control of
the device that the device will execute normally. This behavior may
have side effects. Once C-SPY has regained control of the device, it
will perform a reset of the device and retain control.
19) When programming the Flash, do not set a breakpoint on the
instruction immediately following the write to Flash operation. A
simple work-around to this limitation is to follow the write to Flash
operation with a NOP, and set a breakpoint on the instruction following
the NOP. Refer to FAQ, Debugging #21).
20) The Dump Memory length specifier is restricted to four
hexadecimal digits (0-ffff). This limits the number of bytes that can be
written from 0 to 65535. Consequently, it is not possible to write
memory from 0 to 0xffff inclusive as this would require a length
specifier of 65536 (or 10000h).
21) Multiple internal machine cycles are required to clear and program the
Flash memory. When single stepping over instructions that
manipulate the Flash, control is given back to C-SPY before these
operations are complete. Consequently, C-SPY will update its
memory window with erroneous information. A work around to this
behavior is to follow the Flash access instruction with a NOP, and then
step past the NOP before reviewing the effects of the Flash access
instruction. Refer to FAQ, Debugging #19).
22) Bits that are cleared when read during normal program execution
(i.e., Interrupt Flags) will be cleared when read while being
debugged (i.e., memory dump, peripheral registers).
Within MSP430F43x/44x devices, bits do not behave this way (i.e., the
bits are not cleared by C-SPY read operations).
23) C-SPY cannot be used to debug programs that execute in the
RAM of F12x and F41x devices. A work around to this limitation is to
debug programs in Flash.
24) While single stepping with active and enabled interrupts, it can
appear that only the interrupt service routine (ISR) is active (i.e.,
the non-ISR code never appears to execute, and the single step
operation always stops on the first line of the ISR). However, this
behavior is correct because the device will always process an active
and enabled interrupt before processing non-ISR (i.e., mainline) code.
A work-around for this behavior is, while within the ISR, to disable the
GIE bit on the stack so that interrupts will be disabled after exiting the
ISR. This will permit the non-ISR code to be debugged (but without
interrupts). Interrupts can later be re-enabled by setting GIE in the
status register in the Register window.
On devices with Clock Control, it may be possible to suspend a clock
between single steps and delay an interrupt request.
25) The base (decimal, hexadecimal, etc.) property of Watch Window
variables is not preserved between C-SPY sessions; the base
reverts to Default Format.