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V
X = 0ld
Y = new
VX
L2 cache External memory
Y
DMA
Cache line
6.14C55xSpecificDMARulesandGuidelines
6.14.1SupportingPacked/BurstModeDMATransfers
C55xSpecificDMARulesandGuidelines
DMARule7isarulefortheclientapplicationwriter.Forexternalmemorybuffersthatareacquiredusing
DMAtransfers,thecorrespondingcacheentriesmustbeinvalidatedtoensurethattheyarenotcached.
ForbuffersthataremodifiedusingCPUaccesses,thecorrespondingcacheentriesmustfirstbewritten
backtoexternalmemoryandtheninvalidatedtoensurecachecoherency.
Itisalsoimportantthatthesebuffersareallocatedonacachelineboundaryandbeamultipleofcache
linesinsize.AsshowninSection6.13.4,ifforsomelocationxthatisaccessedbytheDMA,thereisother
datavsharingthesamecacheline,theentirecachelinemaybebroughtintothecachewhenvis
accessed.Locationxwouldthenendupinthecache,whichviolatesthepurposeofDMARule6.
DMARule8
ForC6000algorithms,allbuffersresidinginexternalmemoryinvolvedinaDMAtransfershouldbe
allocatedonacachelineboundaryandbeamultipleofthecachelinelengthinsize.
DMARule8isaddedforalgorithmwriterswhodividebufferssuppliedtothemthroughtheirfunction
interfaceintosmallerbuffers,andthenusethesesmallerbuffersinDMAtransfers.Inthiscase,the
transfermustalsooccuronbuffersalignedonacachelineboundary.Notethatthisdoesnotmeanthe
transfersizeneedstobeamultipleofthecachelinelengthinsize.Instead,the"buffer"containing
memorylocationsinvolvedinthetransfermustbeconsideredasinglebuffer;thealgorithmmustnot
directlyaccesspartofthebufferasperDMARule6.
DMARule9
C6000AlgorithmsshouldnotusestackallocatedbuffersasthesourceordestinationofanyDMA
transfer.
DMARule9isnecessarysincebuffersallocatedonthestackarenotalignedoncachelineboundaries,
andthereisnomechanismtoforcealignment.Furthermore,thisruleisgoodpractice,asithelpsto
minimizeanalgorithm'sstacksizerequirements.
DuetotheperformancerequirementsofcertainC55xandOMAPplatforms,DMAtransfersmustuse
burst-enabled/packedtransfermodesasmuchaspossible.Thebasicproblemisthatifthesourceor
destinationaddressesarenotalignedonaburstboundary,thentheburstmodegetsdisabledby
hardware.DMAGuideline4isintroducedtotransparentlyassistACPY2libraryimplementationsonthe
C55xplatformstooperateinburst-enabled/packedmode.
DMAGuideline4
Tofacilitatehighperformance,C55xalgorithmsshouldrequestDMAtransferswithsourceand
destinationsalignedon32-bitbyteaddresses.
UseoftheDMAResource 70SPRU352G–June2005–RevisedFebruary2007
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