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A.2PerformanceCharacterizationRules
A.3DMARules
PerformanceCharacterizationRules
Rule25—AllC6xalgorithmsmustbesuppliedinlittle-endianformat.(SeeSection5.3.1)
Rule26—AllC6xalgorithmsmustaccessallstaticandglobaldataasfardata.(SeeSection5.3.2)
Rule27—C6xalgorithmsmustneverassumeplacementinon-chipprogrammemory;i.e.,theymust
properlyoperatewithprogrammemoryoperatedincachemode.(SeeSection5.3.3)
Rule28—Onprocessorsthatsupportlargeprogrammodelcompilation,allfunctionaccessesto
independentlyrelocatableobjectmodulesmustbefarreferences.Forexample,intersection
functionreferenceswithinalgorithmandexternalfunctionreferencestoother
eXpressDSP-compliantmodulesmustbefarontheC54x;i.e.,thecallingfunctionmustpushboth
theXPCandthecurrentPC.(SeeSection5.4.2)
Rule29—Onprocessorsthatsupportlargeprogrammodelcompilation,allindependentlyrelocatable
objectmodulefunctionsmustbedeclaredasfarfunctions;forexample,ontheC54x,callersmust
pushboththeXPCandthecurrentPCandthealgorithmfunctionsmustperformafarreturn.(See
Section5.4.2)
Rule30—Onprocessorsthatsupportanextendedprogramaddressspace(pagedmemory),thecode
sizeofanyindependentlyrelocatableobjectmoduleshouldneverexceedthecodespaceavailable
onapagewhenoverlaysareenabled.(SeeSection5.4.2)
Rule31—AllC55xalgorithmsmustdocumentthecontentofthestackconfigurationregisterthatthey
follow.(SeeSection5.5.1)
Rule32—AllC55xalgorithmsmustaccessallstaticandglobaldataasfardata;alsothealgorithms
shouldbeinstantiableinalargememorymodel.(SeeSection5.5.2)
Rule33—C55xalgorithmsmustneverassumeplacementinon-chipprogrammemory;i.e.,theymust
properlyoperatewithprogrammemoryoperatedininstructioncachemode.(SeeSection5.5.3)
Rule34—AllC55xalgorithmsthataccessdatabyB-busmustdocument:theinstancenumberofthe
IALG_MemRecstructurethatisaccessedbytheB-bus(heap-data),andthedata-sectionname
thatisaccessedbytheB-bus(static-data).(SeeSection5.5.4)
Rule35—AllTMX320C28xalgorithmsmustaccessallstaticandglobaldataasfardata;also,the
algorithmshouldbeinstantiableinalargememorymodel.(SeeSection5.7.1)
Rule19—Allalgorithmsmustcharacterizetheirworst-caseheapdatamemoryrequirements(including
alignment).(SeeSection4.1.1)
Rule20—Allalgorithmsmustcharacterizetheirworst-casestackspacememoryrequirements(including
alignment).(SeeSection4.1.2)
Rule21—Algorithmsmustcharacterizetheirstaticdatamemoryrequirements.(SeeSection4.1.3)
Rule22—Allalgorithmsmustcharacterizetheirprogrammemoryrequirements.(SeeSection4.2)
Rule23—Allalgorithmsmustcharacterizetheirworst-caseinterruptlatencyforeveryoperation.(See
Section4.3)
Rule24—Allalgorithmsmustcharacterizethetypicalperiodandworst-caseexecutiontimeforeach
operation.(SeeSection4.4.2)
DMARule1—Alldatatransfermustbecompletedbeforereturntocaller.(SeeSection6.6)
DMARule2—AllalgorithmsusingtheDMAresourcemustimplementtheIDMA2interface.(See
Section6.7)
SPRU352G–June2005–RevisedFebruary2007RulesandGuidelines77
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