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SP605 Hardware User Guide www.xilinx.com 15
UG526 (v1.1.1) February 1, 2010
Detailed Description
References
See the Micron Technology, Inc. DDR3 SDRAM Specification for more information. [Ref 12]
Also, see the Spartan-6 FPGA Memory Controller User Guide. [Ref 3]
T1 MEM1_DQ9 C3 DQ9
U3 MEM1_DQ10 A2 DQ13
U1 MEM1_DQ11 D7 DQ8
W3 MEM1_DQ12 A3 DQ15
W1 MEM1_DQ13 C8 DQ10
Y2 MEM1_DQ14 B8 DQ14
Y1 MEM1_DQ15 A7 DQ12
H2 MEM1_WE_B L3 WE_B
M5 MEM1_RAS_B J3 RAS_B
M4 MEM1_CAS_B K3 CAS_B
L6 MEM1_ODT K1 ODT
K4 MEM1_CLK_P J7 CLK_P
K3 MEM1_CLK_N K7 CLK_N
F2 MEM1_CKE K9 CKE
N3 MEM1_LDQS_P F3 LDQS_P
N1 MEM1_LDQS_N G3 LDQS_N
V2 MEM1_UDQS_P C7 UDQS_P
V1 MEM1_UDQS_N B7 UDQS_N
N4 MEM1_LDM E7 LDM
P3 MEM1_UDM D3 UDM
E3 MEM1_RESET_B T2 RESET_B
Table 1-5: DDR3 Component Memory Connections (Cont’d)
U1 FPGA
Pin
Schematic Net Name
Memory U42
Pin Number Pin Name