Xilinx SP605 Computer Hardware User Manual


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SP605 Hardware User Guide www.xilinx.com 27
UG526 (v1.1.1) February 1, 2010
Detailed Description
Table 1-10: GTP SMA Clock Connections
U1 FPGA Pin Schematic Net Name SMA Pin
C9 SMA_RX_N J35.1
D9 SMA_RX_P J34.1
A8 SMA_TX_N J33.1
B8 SMA_TX_P J32.1
D11 SMA_REFCLK_N J36.1
C11 SMA_REFCLK_P J37.1
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