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SP605 Hardware User Guide www.xilinx.com 23
UG526 (v1.1.1) February 1, 2010
Detailed Description
FMC bypass jumper J19 must be connected between pins 1-2 (bypass) to enable JTAG
access to the FPGA on the basic SP605 board (without FMC expansion modules installed),
as shown in Figure 1-7. When the VITA 57.1 FMC LPC expansion connector is populated
with an expansion module that has a JTAG chain, jumper J19 must be set to connect pins
2-3 in order to include the FMC expansion module's JTAG chain in the main SP605 JTAG
chain.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug.
The JTAG connector (USB Mini-B J4) allows a host computer to download bitstreams to the
FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows
debug tools such as the ChipScope® Pro Analyzer tool or a software debugger to access
the FPGA. The iMPACT software tool can also program the BPI flash via the USB J4
connection. iMPACT can download a temporary design to the FPGA through the JTAG.
This provides a connection within the FPGA from the FPGAs JTAG port to the FPGAs BPI
interface. Through the connection made by the temporary design in the FPGA, iMPACT
can indirectly program the BPI flash from the JTAG USB J4 connector. For an overview on
configuring the FPGA, see “Configuration Options,” page 55.
7. Clock Generation
There are three clock sources available on the SP605.
Oscillator (Differential)
The SP605 has one 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto the board
and wired to an FPGA global clock input.
• Crystal oscillator: Epson EG-2121CA-200.0000M-LHPA
• PPM frequency jitter: 50 ppm
References
See the Epson EG-2121CA Data Sheet for more information. Search EG-2121CA at Epson
Toyocom. [Ref 15]
X-Ref Target - Figure 1-7
Figure 1-7: VITA 57.1 FMC LPC (J2) JTAG Bypass Jumper J19
UG526_07_092409
J19
1
FMC_TDI_BUF
Bypass FMC LPC J2 = Jumper 1-2
Include FMC LPC J2 = Jumper 2-3
H - 1x3
2
SYSACE_TDI
3
FMC_TD0