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MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 51
UG257 (v1.1) December 5, 2007 www.xilinx.com
Operation
R
The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write
(LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E
goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12
or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA
generally has no reason to read information from the display.
Tra nsfer ri ng 8-Bit Data over the 4-Bit Interface
After initializing the display and establishing communication, all commands and data
transfers to the character display are via 8 bits, transferred using two sequential 4-bit
operations. Each 8-bit transfer must be decomposed into two 4-bit transfers, spaced apart
by at least 1 Ps, as shown in Figure 5-6. The upper nibble is transferred first, followed by
the lower nibble. An 8-bit write operation must be spaced least 40 Ps before the next
communication. This delay must be increased to 1.64 ms following a Clear Display
command.
Initializing the Display
After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient 8-
bit PicoBlaze
embedded controller. After initialization, the PicoBlaze controller is available
for more complex control or computation beyond simply driving the display.
Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the
four-bit data interface to the LCD as follows:
x Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 100 Ps or longer, which is 5,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
x Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
x Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
x Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
Display Configuration
After the power-on initialization is completed, the four-bit interface is now established.
The next part of the sequence configures the display:
x Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3E Starter Kit board.
x Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
x Issue a Display On/Off command, 0x0C, to turn the display on and disables the
cursor and blinking.