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Agilent E1439 Programmer's Reference
Functions listed alphabetically
Parameters
id is the VXI instrument session pointer returned by the age1439_init function.
adcLevel is used to set the triggering signal threshold when using the ADC trigger source. This threshold is
(full scale × adclevel/2048), where −2048 ≤adclevel ≤2047. There is hysteresis around the
threshold in order to prevent multiple triggers from a single threshold crossing. Hysteresis is 20
ADC counts, or about 1% full scale.
Use AGE1439_ADC_LEVEL_MAX to set the maximum allowable level.
Use AGE1439_ADC_LEVEL_MIN to set the minimum allowable level.
Use AGE1439_ADC_LEVEL_DEF to set the default ADC trigger threshold.
An accurate value of full scale (in volts) can be found by:
full scale = (age1439_data_scale_get * 2^N)/k
where N = 15 if age1439_data_resolution == AGE1439_12_BIT
N = 29 if age1439_data_resolution == AGE1439_24_BIT
and k = 2 if age1439_filter_decimate == AGE1439_DECIMATE_SHIFT
k = 2 if age1439_data_type == AGE1439_REAL and age1439_frequency_center is non-zero
k = 1 otherwise
adcLevelPtr points to the current value of the adclevel parameter.
trigDelay is the time delay, in units of output samples, between when a trigger is received and the first data
point in the output data.
AGE1439_TRIG_DELAY_MIN selects the minimum allowable trigger delay.
AGE1439_TRIG_DELAY_MAX selects the maximum allowable trigger delay.
AGE1439_TRIG_DELAY_DEF sets the default trigger delay.
Negative values indicate a pre-trigger condition where samples prior to the trigger event are
included in the output data. The amount of pre-trigger delay is limited to the number of samples
which can be saved in the buffer memory. See the age1439_data_setup function description for
the number of bytes used per sample. The delay limits depend on the data type as follows:
If trigDelay is < (Pre-trigger) a bad parameter error is set.
trigDelayPtr points to the current value of the of delay.
genTrig determines whether a module may generate a trigger.
AGE1439_GENERATE_ON enables triggering.
Trigger delay in output samples (DRAMsize in bytes)
24 bit complex
24 bit real
12 bit complex 12 bit real
Post trigger
2^31−12^31−12^31−1
Pre-trigger
48−(DRAMsize/6) 48−(DRAMsize/3) 48−(DRAMsize/1.5)