Filter
Top Products
REV. B
ADuC812
–52–
Parameter Min Typ Max Unit Figure
SPI MASTER MODE TIMING (CPHA = 1)
t
SL
SCLOCK Low Pulsewidth 330 ns 57
t
SH
SCLOCK High Pulsewidth 330 ns 57
t
DAV
Data Output Valid after SCLOCK Edge 50 ns 57
t
DSU
Data Input Setup Time before SCLOCK Edge 100 ns 57
t
DHD
Data Input Hold Time after SCLOCK Edge 100 ns 57
t
DF
Data Output Fall Time 10 25 ns 57
t
DR
Data Output Rise Time 10 25 ns 57
t
SR
SCLOCK Rise Time 10 25 ns 57
t
SF
SCLOCK Fall Time 10 25 ns 57
MOSI
SCLOCK
(CPOL=1)
SCLOCK
(CPOL=0)
t
SH
t
SL
t
SR
t
SF
BIT 6 – 1
LSB IN
t
DR
MISO
t
DAV
t
DF
t
DSU
MSB BIT 6 – 1
LSB
t
DHD
MSB IN
Figure 56. SPI Master Mode Timing (CPHA = 1)