ZEUS Technical Manual Detailed hardware description
© 2007 Eurotech Ltd Issue D 41
PC/104 interface
The ZEUS PC/104 interface is emulated from the PXA270 PC card interface to support
8/16 bit ISA bus style signals. As the interface is an emulation, the ZEUS does not
support some PC/104 features. Please refer to the section Unsupported PC/104
interface features
on page 43 for specific details.
Add-on boards can be stacked via the PC/104 interface to enhance the functionality of
the ZEUS. Eurotech Ltd has an extensive range of PC/104 compliant modules and
these can be used to quickly add digital I/O, analogue I/O, serial ports and motion
control.
The ISA bus is based on the x86 architecture and is not normally associated with RISC
processors. It is generally necessary to modify standard drivers to support any third
party PC/104 modules.
Any PC/104 add-on board attached to the ZEUS is accessible from the PC card
memory space socket 1. The memory map is shown in the following table:
Address Region size Region name
0x30000000 – 0x300003FF 1KByte PC/104 I/O space, 8/16-bit.
0x30000400 – 0x3BFFFFFF - Reserved.
0x3C000000 – 0x3C1FFFFF 16MB PC/104 memory space,
16-bit (or 8-bit write only).
ZEUS PC/104 interface details
The PC/104 bus signals are compatible with the ISA bus electrical timing definitions.
All signals between the PXA270 and the PC/104 are buffered. When the PC/104 bus is
not in use, all output signals with the exception of the clock signals are set to their
inactive state.
The ZEUS provides +5V to a PC/104 add-on board via the J12 and J13 connectors. If
a PC/104 add-on board requires a +12V supply, then +12V must be supplied to the
ZEUS power connector J2 pin 4. If –12V or –5V are required, these must be supplied
directly to the PC/104 add-on board.
The reset signal applied to the PC/104 bus is combination of the RESET_OUT# pin of
PXA270 and an additional circuit that monitors +5V supply.
Due to the specific power management requirements of the PXA270, there is no reset
generated to PXA270 if the +5V supply is below its limits. If the reset is generated to
the PC/104 bus by the +5V monitoring IC, an interrupt can be asserted to PXA270 on
GPIO20.