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ZEUS Technical Manual Detailed hardware description
© 2007 Eurotech Ltd Issue D 45
Panel data bus bit 18-bit TFT 12-bit TFT 9-bit TFT
FPD 7 G2 G0 -
FPD 6 G1 - -
FPD 5 G0 - -
FPD 4 B5 B3 B2
FPD 3 B4 B2 B1
FPD 2 B3 B1 B0
FPD 1 B2 B0 -
FPD 0 B1 - -
GND B0 - -
STN panel data bit mapping to the ZEUS
Panel data bus bit Dual scan colour STN Single scan colour STN Dual scan mono STN
FPD 15 DL7(G) - -
FPD 14 DL6(R) - -
FPD 13 DL5(B) - -
FPD 12 DL4(G) - -
FPD 11 DL3(R) - -
FPD 10 DL2(B) - -
FPD 9 DL1(G) - -
FPD 8 DL0(R) - -
FPD 7 DU7(G) D7(G) DL3
FPD 6 DU6(R) D6(R) DL2
FPD 5 DU5(B) D5(B) DL1
FPD 4 DU4(G) D4(G) DL0
FPD 3 DU3(R) D3(R) DU3
FPD 2 DU2(B) D2(B) DU2
FPD 1 DU1(G) D1(G) DU1
FPD 0 DU0(R) D0(R) DU0
The table below explains the clock signals required for passive and active type
displays:
ZEUS Active display signal (TFT) Passive display signal (STN)
PCLK Clock Pixel Clock
LCLK Horizontal Sync Line Clock
FCLK Vertical Sync Frame Clock
BIAS DE (Data Enable) Bias