Filter
Top Products
ZEUS Technical Manual Detailed hardware description
© 2007 Eurotech Ltd Issue D 62
JTAG and debug access
Debug access to the PXA270 processor is via the JTAG connector J5. A standard ARM
20-pin header is used for the JTAG interface. See J5 – JTAG connector
, page 79, for
details.
Jumper JP7 needs to be inserted to enable the JTAG interface for PXA270 debug. See
section JP7 - JTAG Enable
, page 95 for details.
The Macraigor Wiggler (see www.macraigor.com/wiggler.htm
) and usb2Sprite (see
www.macraigor.com/usb2sprite.htm
) probes have been used to debug the PXA270
processor on the ZEUS. There are many other debug tools that can be interfaced to
the ZEUS for access to the JTAG Interface of the PXA270 processor.
In addition to the PXA270, there are two CPLDs (XC9536XL-CS48 and
XC9572XL-CS48) in the JTAG chain on the ZEUS. The BSDL files can be
found on the www.xilinx.com
web site.