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FUNCTIONAL DESCRIPTION
RRST - Receive FIFO Reset:
When set (logic 1), all bytes in the receiver
FIFO are cleared and the counter is reset. The
shift register is not cleared. RRST is self-
clearing.
FE - FIFO Enable:
When set (logic 1), enables transmitter and
receiver FIFOs. When cleared (logic 0), all
bytes in both FIFOs are cleared. This bit must
be set when other bits in the FIFO control
register are written to or the bits will be
ignored.
D. LINE
CONTROL REGISTER
+------+
D7 | DLAB |----- Divisor latch access bit
+------+
D6 | BKCN |----- Break control
+------+
D5 | STKP |----- Stick parity
+------+
D4 | EPS |----- Even parity select
+------+
D3 | PEN |----- Parity enable
+------+
D2 | STB |----- Number of stop bits
+------+
D1 | WLS1 |--+
+------+ +-- Word length select
D0 | WLS0 |--+
+------+
Figure 8. Line Control Register bit definitions.
DLAB - Divisor Latch Access Bit:
DLAB must be set to logic 1 to access the baud
rate divisor latches. DLAB must be set to logic
0 to access the receiver buffer, transmitting
holding register and interrupt enable register.
BKCN - Break Control:
When set (logic 1), the serial output (SOUT) is
forced to the spacing state (logic 0).
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