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AUD RATE SELECTION
J1 J1
+-----------+ +-----------+
1| o o+ o |4 1| o--o o |4
2| o o+ o |5 2| o o--o |5
+-----------+ +-----------+
(a) ÷1 input clock (b) ÷2 input clock
J1 J1
+-----------+ +-----------+
1| o o--o |4 1| o+ o--o |4
2| o--o o |5 2| o+ o--o |5
+-----------+ +-----------+
(c) ÷5 input clock (d) ÷10 input clock
Figure 14. Input clock frequency options. For
compatibility, the jumper should be set at
÷10 ( 18.432 MHz ÷ 10 = 1.8432 MHz ).
The baud rate may now be calculated using the
equation
crystal frequency
baud rate = -------------------
16 x divider x DL
where
divider = the clock divider setting of jumper J1
DL = the value programmed into the baud rate
divisor latches of the 16550.
+-----------+-------------+-----------------------+
| Desired | Divisor | Error Between Desired |
| Baud Rate | Latch Value | and Actual Value (%) |
+-----------+-------------+-----------------------+
| 110 | 1047 | 0.026 |
| 300 | 384 | - |
| 1200 | 96 | - |
| 2400 | 48 | - |
| 4800 | 24 | - |
| 9600 | 12 | - |
| 19200 | 6 | - |
| 38400 | 3 | - |
| 56000 | 2 | 2.86 |
+-----------+-------------+-----------------------+
Figure 15. Divisor latch settings for common baud
rates using a 1.8432 MHz input clock.
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