Filter
Top Products
FUNCTIONAL DESCRIPTION
H. SCRATCHPAD
REGISTER
This register is not used by the 16550. It may be
used by the programmer for data storage.
IV. FIFO
INTERRUPT MODE OPERATION
1. The receive data interrupt is issued when the FIFO
reaches the trigger level. The interrupt is
cleared as soon as the FIFO falls below the trigger
level.
2. The interrupt identification register's receive data
available indicator is set and cleared along with
the receive data interrupt above.
3. The data ready indicator is set as soon as a
character is transferred into the receiver FIFO and
is cleared when the FIFO is empty.
V. BAUD
RATE SELECTION
The 16550 UART determines the baud rate of the
serial output from a combination of the clock input
frequency and the value written to the divisor latches.
Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use
an input clock of 1.8432 MHz. To increase versatility,
the DS-2000 uses an 18.432 MHz clock and a frequency
divider circuit to produce the standard clock frequency.
Jumper block J1 is used to set the frequency of the
16550. It may be connected to divide the clock input by
1, 2, 5, or 10. For compatibility, J1 should be
configured to divide by 10 as shown in figure 14(d).
iii